High Performance Computing (HPC) MCQ's




Question 1 :
For inter processor communication the miss arises are called

  1. hit rate
  2. coherence misses
  3. comitt misses
  4. parallel processing
  

Question 2 :
Communicating a message of size m over an uncongested network takes time ts + tmw

  1. TRUE
  2.  False
  

Question 3 :
If n is a power of two, we can perform this operation in ____ steps by propagating partial sums up a logical binary tree of processors.

  1. logn
  2. nlogn
  3. n
  4. n^2
  

Question 4 :
MPI_Comm_size

  1. Returns number of processes
  2. Returns number of line
  3. Returns size of program
  4. Returns value of instruction
  

Question 5 :
Parallel computing means to divide the job into several __________

  1. Bit
  2. Data
  3. Instruction
  4. Task
  

Question 6 :
A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______ .

  1. Super-scaling
  2. Pipe-lining
  3. Parallel computation
  4. serial computation
  

Question 7 :
Mpi_Recv used for

  1. reverse message
  2. receive message
  3. forward message
  4. Collect message
  

Question 8 :
In which system desire HPC

  1. Adaptivity
  2. Transparency
  3. Dependency
  4. Secretivte
  

Question 9 :
Pipe-lining is a unique feature of _______.

  1. CISC
  2. RISC
  3. ISA
  4. IANA
  

Question 10 :
To increase the speed of memory access in pipelining, we make use of _______

  1. Special memory locations
  2. Special purpose registers
  3. Cache
  4. Buffer
  

Question 11 :
What is the execution time per stage of a pipeline that has 5 equal stages and a mean overhead of 12 cycles

  1. 2 cycles
  2. 3 cycles
  3. 5 cycles
  4. 4 cycles
  

Question 12 :
The main difference between the VLIW and the other approaches to improve performance is ___________

  1. increase in performance
  2. Lack of complex hardware design
  3. Cost effectiveness
  4. latency
  

Question 13 :
The stalling of the processor due to the unavailability of the instructions is called as ___________

  1. Input hazard
  2. data hazard
  3. structural hazard
  4. control hazard
  

Question 14 :
If the value V(x) of the target operand is contained in the address field itself, the addressing mode is

  1. Immediate
  2. Direct
  3. Indirect
  4. Implied
  

Question 15 :
To which class of systems does the von Neumann computer belong

  1. SIMD
  2. MIMD
  3. MISD
  4. SISD
  

Question 16 :
The parallelism across branches require which scheduling

  1. Global scheduling
  2. Local Scheduling
  3. post scheduling
  4. pre scheduling
  

Question 17 :
The Prefix Sum Operation can be implemented using the_

  1. All-to-all broadcast kernel.
  2.  All-to-one broadcast kernel.
  3.  One-to-all broadcast Kernel
  4. Scatter Kernel
  

Question 18 :
The contention for the usage of a hardware device is called ______

  1. data hazard
  2. Stalk
  3. Deadlock
  4. structural hazard
  

Question 19 :
The need for parallel processor to increase speedup

  1. Moores Law
  2. Minsky conjecture
  3. Flynns Law
  4. Amdhals Law
  

Question 20 :
 A single control unit that dispatches the same Instruction to various processors is__

  1. SIMD
  2. SPMD
  3. MIMD
  4. None of above
  

Question 21 :
When every caches hierarchy level is subset of level which futher away from the processor

  1. Synchronous
  2. Atomic synschronous
  3. Distrubutors
  4. Multilevel inclusion
  

Question 22 :
Writing parallel programs is referred to as

  1. Parallel computation
  2. parallel development
  3. parallel programing
  4. Parallel processing
  

Question 23 :
The gather operation is exactly the inverse of the_

  1. Scatter operation
  2.  Broadcast operation
  3.  Prefix Sum
  4. Reduction operation
  

Question 24 :
Uniprocessor computing devices is called__________.

  1. Grid computing
  2. Centralized computing
  3. Parallel computing
  4. Distributed computing
  

Question 25 :
hypercube has_

  1. 2d nodes
  2.  2d nodes
  3.  2n Nodes
  4. N Nodes
  

Question 26 :
The computer architecture aimed at reducing the time of execution of instructions is ________.

  1. CISC
  2. RISC
  3. SPARC
  4. ISA
  

Question 27 :
The situation wherein the data of operands are not available is called ______

  1. stock
  2. Deadlock
  3. data hazard
  4. structural hazard
  

Question 28 :
Speedup, in theory, should be ______ bounded by p

  1. lower
  2. upper
  3. left
  4. right
  

Question 29 :
Tree networks suffer from a communication bottleneck at higher levels of the tree. This network, also called a _________ tree.

  1. fat
  2. binary
  3. order static
  4. heap tree
  

Question 30 :
_____processors rely on compile time analysis to identify and bundle together instructions that can be executed concurrently

  1. VILW
  2. LVIW
  3. VLIW
  4. VLWI
  
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