Microprocessor MCQ's




Question 1 :
Which register of 8259 PIC stores all interrupt level that are requesting for interrupt service?

  1. IMR
  2. ISR
  3. Control Register
  4. IRR
  

Question 2 :
Which port is used for the generation of handshake lines in mode 1 or mode 2?

  1. Port B lower
  2. Port B
  3. Port A Upper
  4. Port C
  

Question 3 :
Select the correct difference between compare and subtract instruction of 8086.

  1. Compare instruction stores the result of comparison
  2. Compare instruction shows result using flags and doesn’t store result
  3. Subtraction doesn’t store result
  4. Subtraction shows result using flags and doesn’t store result
  

Question 4 :
In 8253 PIT device, the counter starts counting only if ?

  1. GATE signal is low
  2. GATE signal is high
  3. CLK signal is low
  4. CLK signal is high
  

Question 5 :
The speed of integer arithmetic of Pentium is increased to a large extent by?

  1. 4-stage pipelines
  2. superscalar and super pipelined architecture
  3. superscalar architecture
  4. on-chip floating point unit
  

Question 6 :
If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called as?

  1. Maskable interrupt
  2. Non-maskable interrupt
  3. Maskable interrupt and Non-maskable interrupt
  4. Interrupt Request
  

Question 7 :
When an interrupt occurs, it breaks the execution of current instruction and diverts its execution to one of the following?

  1. Interrupt service routine
  2. Counter word register
  3. Execution unit
  4. control unit
  

Question 8 :
On the execution of CMPSB contents of which segment compared with contents of which segment?

  1. CS - DS
  2. DS - ES
  3. DS - DS
  4. ES - ES
  

Question 9 :
Select the correct difference between compare and subtract instruction of 8086

  1. Compare instruction stores the result of comparison
  2. Compare instruction shows result using flags and doesn’t store result
  3. Subtraction doesn’t store result
  4. Subtraction shows result using flags and doesn’t store result
  

Question 10 :
80386 support which type of descriptor table from the following?

  1. TDS
  2. ADT
  3. GDT
  4. MDS
  

Question 11 :
How many flags are active in flag register of 80386?

  1. 9
  2. 13
  3. 12
  4. 10
  

Question 12 :
What will be the 8-bit command to mask IR6, IR7 and unmask all other interrupts of 8259 using OCW1?

  1. A0H
  2. C0H
  3. D0H
  4. 0CH
  

Question 13 :
Which addressing mode is being used in the 8086 given instruction? MOV [BX],DL

  1. Direct Addressing Mode
  2. Register Indirect Addressing Mode
  3. Register Addressing Mode
  4. Immediate Addressing Mode
  

Question 14 :
Which type of descriptor table from the following is supported by 80386 DX ?

  1. TDS
  2. ADT
  3. GDT
  4. MDS
  

Question 15 :
The size of Segment address, offset address - physical address are ________ bits each in 8086 microprocessor.

  1. 8,8 - 16
  2. 8,16 - 20
  3. 16,16 - 20
  4. 8,8 - 8
  

Question 16 :
Which instruction makes the 8086 processor check the TEST* pin (* indicates active low signal)?

  1. WAIT
  2. ESC
  3. LOCK
  4. HLT
  

Question 17 :
The mechanism that determines whether a floating point operation will be executed without creating any exception is known as?

  1. Multiple Instruction Issue
  2. Multiple Exception Issue
  3. Safe Instruction Recognition
  4. Safe Exception Recognition
  

Question 18 :
In 8086, when the carry is generated from D3 bit (of D7-D0) ,flag set condition is shown with which flag?

  1. Auxiliary carry
  2. Carry flag
  3. Overflow flag
  4. Trap flag
  

Question 19 :
In PUSH instruction, after each execution of the instruction, the stack pointer is?

  1. incremented by 1
  2. decremented by 1
  3. incremented by 2
  4. decremented by 2
  

Question 20 :
ICW1 of single 8259 which is edge triggered will be?

  1. 0BH
  2. 13H
  3. 11H
  4. 40H
  

Question 21 :
Which is the 8086 instruction that copies content of flag register on to the stack?

  1. PUSH
  2. POP
  3. PUSHF
  4. POPF
  

Question 22 :
What are the three modules in the SPARC processor?

  1. IU, FPU, CU
  2. SP, DI, SI
  3. AX, BX, CX
  4. CU, CH, CL
  

Question 23 :
Which is a not part of Bus Interface Unit

  1. Instruction Queue
  2. Segment Registers
  3. Address conversion mechanism
  4. ALU
  

Question 24 :
What is used to implement the multiple branch prediction in Pentium processor?

  1. control unit
  2. bus interface unit
  3. branch instruction register
  4. branch target buffer
  

Question 25 :
Segment currently being accessed by 8086 is indicated by which status register?

  1. s3 - s4
  2. s0 - s1
  3. s5 - s6
  4. s1 - s2
  

Question 26 :
How linear address is calculated?

  1. effective address + segment base address
  2. effective address + Physical address
  3. Linear address + offset address
  4. Linear address + physical address
  

Question 27 :
Which one of the following is used to check output of every single instruction?

  1. Auxiliary carry
  2. carry flag
  3. overflow flag
  4. Trap flag
  

Question 28 :
What is the memory data bus width in Pentium?

  1. 16 bit
  2. 32 bit
  3. 64 bit
  4. 48 bit
  

Question 29 :
Which segment registers and offset registers combinations are true for 8086 processors:

  1. CS-IP; DS-SI; ES-DI; SS-SP
  2. CS-IP; DS-SI; ES-EI; SS-BP
  3. CS-SP; ES-SI; DS-DI; SS-BP
  4. CS-IP; DS-DI; ES-SI; SS-BP
  

Question 30 :
The status of the pending interrupts is checked at

  1. the end of main program
  2. the end of each instruction cycle
  3. the end of all the interrupts executed
  4. the beginning of every interrupt
  
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