Microprocessor MCQ's




Question 31 :
In 8257 (DMA), each of the four channels has?

  1. a pair of two 8-bit registers
  2. a pair of two 16-bit registers
  3. one 16-bit register
  4. one 8-bit register
  

Question 32 :
Which unit provides a four level protection mechanism for system code and data against application program in 80386?

  1. Paging Unit
  2. Segmentation Unit
  3. Execution Unit
  4. Central Processing Unit
  

Question 33 :
The procedure defined as ‘FAR’ procedure is associated with how many bytes of starting address?

  1. 4
  2. 6
  3. 8
  4. 16
  

Question 34 :
What is the contents of the register after execution of following: MOV AL, E9H NEG AL

  1. 16
  2. 15
  3. 17
  4. 26
  

Question 35 :
How many bits logical address is supported by 80386 DX microprocessor?

  1. 32
  2. 20
  3. 64
  4. 48
  

Question 36 :
How many bits logical address is supported by 80386?

  1. 32
  2. 20
  3. 64
  4. 48
  

Question 37 :
Which instruction among the following unconditionally transfers the control of execution to the provided address?

  1. CALL
  2. IRET
  3. JNC
  4. JMP
  

Question 38 :
Which of the following is a class of architecture of MII (multiple instruction issue) in Pentium?

  1. super pipelined architecture
  2. multiple instruction issue
  3. very small instruction word architecture
  4. super scalar architecture
  

Question 39 :
Which mode does 8086 microprocessor operate in if MN/MX is low?

  1. Minimum Mode
  2. Maximum mode
  3. Control Mode
  4. Execute Mode
  

Question 40 :
Which of the following is an example of an external interrupt?

  1. divide by zero interrupt
  2. overflow interrupt
  3. keyboard interrupt
  4. type2 interrupt
  

Question 41 :
The 80386DX has an address bus of n Address lines?

  1. 8 address lines
  2. 16 address lines
  3. 32 address lines
  4. 64 address lines
  

Question 42 :
Which instruction is used to invert each bit of the destination?

  1. AND
  2. NOR
  3. NOT
  4. OR
  

Question 43 :
The SPARC Processor consists of ___ bits of registers?

  1. 8
  2. 16
  3. 32
  4. 64
  

Question 44 :
What will be the starting and ending offset address (or range) if the size of the segment is 64 KB?

  1. 0000H to 7FFFH
  2. 0000H to FFFFH
  3. 8000H to FFFFH
  4. 00000H to FFFFFH
  

Question 45 :
In Pentium, the percentage of hits to the total cache access is given by?

  1. Hit Ratio
  2. Accuracy
  3. Efficiency
  4. Precision
  

Question 46 :
Which is the address decoding technique where all remaining address lines are used to generate the Chip select signal?

  1. Partial
  2. Absolute
  3. Block
  4. non linear
  

Question 47 :
Which is the main feature provided by Pentium?

  1. superscalar architecture
  2. Multithreading architecture
  3. Multioperational architecture
  4. superscalar and super pipelined architecture
  

Question 48 :
Which offset address register is used to generate 20 bit physical address for Code Segment in 8086?

  1. Stack Pointer Register
  2. Base Pointer Register
  3. Source Index Register
  4. Instruction Pointer Register
  

Question 49 :
In 8255, Bidirectional I/O mode is applicable for which port?

  1. Port A
  2. Port B
  3. Port C
  4. Port B lower
  

Question 50 :
In SPARC, a register bank comprises of how many registers?

  1. 8
  2. 16
  3. 32
  4. 10
  
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